View CS61318_2151890.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS61318 e1 line interface unit features n e1 line interface unit n no crystal needed for jitter attenuation n meets ctr-12/tbr-12 jitter tolerance and attenu- ation requirements n meets itu-t g.775 requirements for los and ais n meets the bs6450 transmitter short-circuit requirements for e1 applications n awg for user programmable pulse shapes n line quality monitoring function n tx driver high impedance / low power control n ais and los monitoring n generation and detection of loop up / loop down signaling n selectable hdb3 encoding/decoding n selectable unipolar or bipolar i/o n compliant with: itu-t recommendations: g.703, g.732, g.775, i.431 etsi ets 300 011, 300 233, ctr 12, tbr 13 tr-net-00499 description the CS61318 is an e1 primary rate line interface unit. this device combines the complete analog transmit and receive circuitry for a single, full-duplex interface e1 rates. the device provides jitter attenuation compliant to ctr12/tbr13 without requiring an external crystal. al- so, the CS61318 is pin and function compatible with the level one lxt318. in addition to a basic hardware control mode, a host mode is available that gives the user an enhanced func- tionality via a serial microprocessor interface. the extended features include custom pulse shape genera- tion, ais and los monitoring functions, signal strength monitoring, and generation and detection of loop up and loop down codes. ordering information CS61318-il 28-pin plcc CS61318-ip 28-pin pdip tclk tdata/tpos ubs/tneg jasel rclk rdata/rpos bpv/rneg int/nloop los 2 3 4 e n c o d e r 11 remote loopback 8 7 6 d e c o d e r 23 12 inband nloop & los processor receive clock generator 9 10 xtalin xtalout 5 21221415 mode rv+ rgnd tgnd tv+ jitter atten timing & data recovery los/ nloop clear registers & control logic taos enable jitter atten transmit timing & control pulse shaping circuitry rom / ram line drivers serial port lloop enable local loopback (analog) equalizer control slicers & peak detect noise & crosstalk filters magnitude equalizer agc 13 16 28 26 27 24 25 18 19 20 1 ttip tring clke/taos cs/rloop sclk/lloop sdi/lbo1 sdo/lbo2 latn rtip rring mclk local loopback (digital) ds441pp2 aug 99
CS61318 2 ds441pp2 table of contents 1 characteristics and specifications ......................................................................... 4 absolute maximum ratings ........................................................................................... 4 recommended operating conditions ....................................................................... 4 digital characteristics ................................................................................................. 4 analog specifications .................................................................................................... 5 e1 switching characteristics ..................................................................................... 6 serial port switching characteristics.................................................................. 7 2 theory of operation ........................................................................................................ 8 2.1 operating modes ........................................................................................................... .... 8 2.2 master clocks ............................................................................................................. ....... 8 2.3 transmitter ............................................................................................................... .......... 8 2.4 transmit all ones select .................................................................................................. .9 2.4.1 receiver ................................................................................................................ 9 2.4.2 clock recovery ..................................................................................................... 9 2.4.3 jitter tolerance ..................................................................................................... 9 2.4.4 receiver line attenuation indication ..................................................................... 9 2.5 jitter attenuator ......................................................................................................... ........ 9 2.6 receiver loss of signal ................................................................................................... 10 2.7 local loopback ............................................................................................................ .... 10 2.8 remote loopback ........................................................................................................... .11 2.9 network loopback .......................................................................................................... .11 2.10 alarm indication signal .................................................................................................. 11 2.11 serial interface ......................................................................................................... ...... 11 2.11.1 control register 1: address 0x10 ............................................................................... 13 2.11.2 control register 2: address 0x11 ............................................................................. 14 2.11.3 equalizer gain (eqgain): address 0x12 ................................................................... 14 2.11.4 arbitrary waveform ram address (ram): address 0x13 .......................................... 14 2.12 interrupts ............................................................................................................... ......... 15 2.13 power on reset / reset ................................................................................................ 15 2.14 power supply ............................................................................................................. .... 15 3 arbitrary waveform generation ............................................................................. 16 4 pin description ............................................................................................................ ...... 19 4.1 power supplies ............................................................................................................ .... 20 4.2 oscillator ................................................................................................................ .......... 20 4.3 control ................................................................................................................... .......... 20 4.4 status .................................................................................................................... ........... 21 4.5 serial control interface .................................................................................................. .. 21 4.6 data input/output ......................................................................................................... ... 22 5 package dimensions ........................................................................................................ 2 4 6 applications ............................................................................................................... ........ 26 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provid e d as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or t rade secrets. no part of this publi- cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechan ical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by t he user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any mea ns (electronic, mechanical, photo- graphic, or otherwise) without the prior written consent of cirrus logic, inc. furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a li st of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
CS61318 ds441pp2 3 list of figures figure 1. signal rise and fall characteristics ................................................................. 6 figure 2. recovered clock and data switching characteristics ...................................... 6 figure 3. transmit clock and data switching characteristics ......................................... 6 figure 4. serial port write timing diagram ..................................................................... 7 figure 5. serial port read timing diagram ..................................................................... 7 figure 6. mask of the pulse at the 2048 kbps interface ................................................... 8 figure 7. latn pulse width encoding ........................................................................... 10 figure 8. typical jitter transfer function ....................................................................... 10 figure 9. input/output timing (showing address 0x10) ................................................. 12 figure 10. phase definition of arbitrary waveform ........................................................ 16 figure 11. example of summing of waveforms ............................................................. 16 figure 12. CS61318 host mode operation .................................................................... 26 figure 13. hardware mode configuration ..................................................................... 27 list of tables table 1. data output/clock relationship ........................................................................... 9 table 2. register map..................................................................................................... 12 table 3. control register 1 (0x10) decoding................................................................... 15 table 4. CS61318 diagnostic mode availability .............................................................. 17 table 5. transformer specification .................................................................................. 18 table 6. recommended tranformers for the CS61318 ................................................... 18
CS61318 4 ds441pp2 1 characteristics and specifications absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. transient currents of up to 100 ma will not cause scr latch-up. also ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. recommended operating conditions notes: 2. tv+ must not exceed rv+ by more than 0.3 v. 3. power consumption figures assume device is driving line load over operating temperature range. the consumption of both the ic and the load are included. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 4. typical consumption corresponds to 50% ones density and medium line length at 5.0 v. 5. maximum consumption corresponds to 100% ones density and maximum line length at 5.25 v. digital characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0 v 5%; gnd = 0 v) notes: 6. this specification guarantees ttl compatibility (v oh = 2.4 v @ i out = -40 m a). 7. output drivers are ttl compatible and will drive cmos logic levels into a cmos load. parameter symbol min max units dc supply (referenced to rgnd=tgnd=0 v) rv+ tv+ - - 6.0 (rv+) + 0.3 v v input voltage, any pin v in rgnd-0.3 (rv+) + 0.3 v input current, any pin (note 1) i in -10 10 ma ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c parameter symbol min typ max units dc supply (note 2) rv+, tv+ 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c power consumption, long haul (notes 3,4,5) p c -390630mw power consumption, short haul (notes 3,4,5) p c -480710mw parameter symbol min typ max units high-level input voltage (note 6) pins 1-4, 24-28 v ih 2.0 - - v low-level input voltage (note 6) pins 1-4, 24-28 v il --0.8v high-level output voltage (notes 6, 7) i out = -40 m a pins 6-8, 25 v oh 2.4 - - v low-level output voltage (notes 6, 7) i out = 1.6 ma pins 6-8, 25 v ol --0.4v input leakage current - - 10 m a
CS61318 ds441pp2 5 analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0 v 5%; gnd = 0 v) notes: 8. using a 0.47 f capacitor in series with the primary of a transformer recommended in the applications section. 9. pulse amplitude measured at the secondary of the transformer across a 75 w load. 10. pulse amplitude measured at the secondary of the transformer across a 120 w load. 11. assuming that jitter free clock is input to tclk. 12. not production tested. parameters guaranteed by design and characterization. 13. measured broadband through a 0.5 w resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern. 14. data decision threshold established after the receiver equalizer filters pulse overshoot and undershoot. 15. jitter tolerance for 0 db input signal level. jitter tolerance increases at lower frequencies. parameter min typ max units transmitter ami output pulse amplitudes (note 8) e1, 75 w (note 9) e1, 120 w (note 10) 2.14 2.7 2.37 3.0 2.6 3.3 v v transmitter output impedance transformer turns ratio = 1:2 low z, long haul 1.5 w jitter added by the transmitter (notes 11,12) 10 hz - 8 khz 8k hz - 40 khz 10 hz - 40 khz broad band - - - - 0.015 0.015 0.015 0.020 - - - - ui ui ui ui positive to negative pulse imbalance (notes 8, 12) - 0.2 0.5 db transmitter short circuit current (notes 8, 13) - - 50 ma rms receiver rtip/rring input impedance - 20k - w sensitivity below dsx (0 db = 3.0 v) -36 48 - - - - db mv sensitivity below g.703 (0 db = 2.4 v) e1 - short haul -15 430 - - - - db mv loss of signal threshold - -42 - db data decision threshold (note 14) 45 50 55 % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter tolerance - short haul (note 15) 10 khz - 100 khz (note 12, 15) 2 khz (note 12, 15) 10 hz and below 0.35 6.0 300 - - - - - - ui ui ui receiver input jitter tolerance - long haul 10 khz - 100 khz (note 12, 15) 1 hz 0.35 138 - - - - ui ui
CS61318 6 ds441pp2 e1 switching characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0 v 5%; gnd = 0 v; inputs: logic 0 = 0 v, logic 1 = rv+; see figures 1, 2, & 3) notes: 16. mclk provided by an external source to tclk. 17. rclk duty cycle will be 62.5% or 37.5% when jitter attenuator fifo limits are reached. 18. at max load of 1.6ma and 50pf. 19. host mode (clke = 1). 20. host mode (clke = 0). parameter symbol min typ max units tclk frequency f tclk -2.048-mhz tclk duty cycle (note12) t pwh2 /t pw2 40 50 60 % mclk frequency (note 16) f mclk -2.048-mhz rclk duty cycle (note 17) t pwh1 /t pw1 45 50 55 % rise time, all digital outputs (note 18) t r --85ns fall time, all digital outputs (note 19) t f --85ns tpos/tneg to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg hold time t h2 25 - - ns rpos/rneg valid before rclk falling (note 19) t su1 100 194 - ns rpos/rneg valid before rclk rising (note 20) t su1 100 194 - ns rpos/rneg valid after rclk falling (note 19) t h1 100 194 - ns rpos/rneg valid after rclk rising (note 20) t h1 100 194 - ns any digital output t r t f 10% 10% 90% 90% figure 1. signal rise and fall characteristics rclk t pw1 t pwl1 t pwh1 (clke = 1) (clke = 0) rclk rpos rneg su1 h1 tt figure 2. recovered clock and data switching characteristics tclk tpos/tneg t su2 t h2 t pwh2 t pw2 figure 3. transmit clock and data switching characteristics
CS61318 ds441pp2 7 serial port switching characteristics (ta = -40 to 85 c; tv+, rv+ = 5v 5%; inputs: logic 0 = 0 v, logic 1 = rv+) notes: 21. output load capacitance = 50 pf parameter symbol min typ max units sdi to sclk setup time t dc 50 - - ns sclk to sdi hold time t cdh 50 - - ns sclk low time t cl 240 - - ns sclk high time t ch 240 - - ns sclk rise and fall time t r , t f - - 50 ns cs to sclk setup time t cc 50 - - ns sclk to cs hold time t cch 50 - - ns cs inactive time t cwh 250 - - ns sclk to sdo valid (note 21) t cdv --200ns cs to sdo high z t cdz -100-ns t dc t cc lsb lsb msb control byte data byte cs sclk sdi t ch t cwh t cch t cdh t cl t cdh figure 4. serial port write timing diagram high z cs sclk sdo clke = 1 sdi cdv t cdv t cdz t sdo clke = 0 last addr bit d0 d1 d6 d7 d0 d1 d6 d7 figure 5. serial port read timing diagram
CS61318 8 ds441pp2 2 theory of operation the CS61318 e1 line interface is a fully integrated transceiver designed for 2.048 mbps e1 operation. the device provides an interface to twisted pair or co-axial media through standard pulse transformers and matching resistors. for added flexibility, the device can be controlled through a serial micropro- cessor interface (host mode operation) or via de- vice pins (hardware mode). 2.1 operating modes the CS61318 can be controlled in stand-alone hardware interface mode (mode pin is low), or by a microcontroller in serial host mode (mode pin is high). additional functionality is available in the host mode as described in the serial interface sec- tion. 2.2 master clocks the CS61318 requires a reference clock for the re- ceiver and the jitter attenuator. a 2.048 mhz exter- nal clock can be input to mclk, or a 4x crystal can be connected to the on-chip oscillator. this fre- quency reference should be within + 50 ppm of the nominal operating frequency. jitter and wander on the reference clock will degrade jitter attenuation and receiver jitter tolerance. if mclk is provided, the crystal oscillator is ignored. 2.3 transmitter the transmitter accepts digital e1 input data and drives appropriately shaped ami (alternate mark inversion) pulses onto a transmission line through a transformer. the transmit data (tpos & tneg or tdata) is sampled on the falling edge of the input clock, tclk. tying tneg high for more than 16 tclk cycles enables unipolar i/o mode. this changes tpos to tdata, rpos to rdata, and rneg to bpv. in this mode the hdb3 encoder and decoder is en- abled on both the receive and transmit paths. the CS61318 drives a 75 w or 120 w line through the appropriate transformer and matching resistors. a summary of transformer and resistor configura- tions is given in the applications section at the end of this datasheet. using the recommended circuits will produce e1 pulses compliant to the g.703 tem- plate shown in figure 6. custom transmit pulse shapes may be implemented by writing pulse shape coefficients to on-board pulse shape registers. custom pulses may be used to correct for pulse shape degradation or distortion caused by improper termination, suboptimal inter- connect wiring, or loading from external compo- nents such as high voltage protection devices. use of this feature is described in the arbitrary wave- form generation section. the CS61318 will detect the absence of tclk, and will force ttip and tring to high impedance af- ter 175 bit periods, preventing transmission when 269 ns 244 ns 194 ns 219 ns 488 ns nominal puls e 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage figure 6. mask of the pulse at the 2048 kbps interface
CS61318 ds441pp2 9 data input is not present. in host mode, the trans- mitter can be set to high impedance by setting the txhiz bit, cr2.1, to 1. when any transmit control bit (taos or lloop) is toggled, the transmitter outputs will require ap- proximately 22 bit periods to stabilize. the trans- mitter will take longer to stabilize when rloop is selected because the timing circuitry must adjust to the new frequency. 2.4 transmit all ones select the transmitter provides for all ones insertion at the frequency of tclk. if tclk is absent, then mclk is used (or the quartz crystal generated fre- quency in the absence of mclk). transmit all ones is selected when taos, pin 28, (cr1.7 = 1, in host mode) goes high, and causes continuous ones to be transmitted on the line (ttip and tring). when taos is active, the tpos and tneg (tdata) inputs are ignored. if remote loopback is in effect, any taos request will be ignored. 2.4.1 receiver the receiver extracts data and clock from the input signal and outputs clock and synchronized data. the long haul receiver can receive signals over the entire range down to -36db at e1 rates. the in- coming pulses are amplified, equalized and filtered before being fed to the comparator for peak detec- tion, slicing and data recovery. the clock and data recovery circuit exceeds the jitter tolerance specifi- cations of itu-t g.823 and etsi ctr12. the rtip and rring inputs are biased to an interme- diate dc level and treat the input signal differen- tially. 2.4.2 clock recovery the clock recovery circuit is a third-order phase- locked loop. the clock and data recovery circuit is tolerant of long strings of consecutive zeros, and will successfully receive a 1-in-175, jitter-free in- put signal. data on rpos and rneg (rdata), is stable and may be latched using the falling edge of recovered clock, rclk. in host mode, clke, pin 28, deter- mines the clock polarity for which output data is stable and valid as shown in table 1. when clke is high, rpos and rneg (rdata) are valid on the falling edge of rclk. when clke is low, rpos and rneg are valid on the rising edge of rclk. table 1. data output/clock relationship 2.4.3 jitter tolerance the CS61318 has excellent jitter tolerance, accept- ing as much as 0.35ui of jitter from 10 khz to 100 khz without error. 2.4.4 receiver line attenuation indica- tion the latn pin, pin 18, outputs a coded signal that represents the signal level at the input of the receiv- er. as shown in figure 7, the latn output is mea- sured against rclk to provide the signal level in 7.5 db increments. in host mode, the receive input signal level can be read from the equalizer gain register, address 0x12, to greater resolution, divid- ing the input range into 20 steps of 2 db incre- ments. 2.5 jitter attenuator jitter attenuation can be implemented in either the transmit (jasel is low) or receive (jasel is high) mode (pin 5) clke (pin 28) data clock clock edge for valid data low dont care rpos rneg rclk rising high low rpos rneg sdo rclk rclk sclk rising rising falling high high rpos rneg sdo rclk rclk sclk falling falling rising
CS61318 10 ds441pp2 paths, or it can be eliminated from the circuit by setting the xtalin, pin 9, high. the jitter attenu- ator on the CS61318 does not require a crystal, and can be activated by setting xtalin, pin 9, low (preferred) or by floating pin 9. the jitter attenuators corner frequency is approxi- mately 1.25 hz in order to comply with etsi 300 011, ctr12, and recommendation i.431. a typical jitter attenuation graph is shown in figure 8. 2.6 receiver loss of signal the receiver will indicate loss of signal by setting los, pin 12 high (cr1.0 = 1 in host mode), upon power up, reset, when receiver gain is maximized, or upon receiving 175+/-15 consecutive zeros. re- ceived zeros are counted based on recovered clock cycles. when in the los state, received data is not output from rpos/rneg (rdata); but is squelched until the device comes out of los. the los condition is exited using itu-t g.775 crite- ria, namely 12.5% ones density for 175+/-75 bit pe- riods with no more than 100 consecutive zeros. the receiver recovers signals down to -36 db, and los will be declared below this signal level. in los, the rclk frequency depends on whether mclk is applied, and whether the jitter attenuator is in the transmit or receive path. if the jitter atten- uator is in the receive path, the jitter attenuator will hold over the average incoming data frequency pri- or to los. rpos (rdata) and rneg pins are forced low upon los. when the jitter attenuator is in the transmit path or not used, the clock recovery is referenced to mclk, if provided, or the crystal oscillator. the frequency of rclk in this case will simply remain slaved to the clock reference upon loss of data. the recovered clock remains as a 50% duty cycle clock. 2.7 local loopback local loopback is selected by setting lloop, pin 27, high (cr1.6 = 1 in host mode). selecting local loopback causes clock and data presented on tclk, tpos/tneg (tdata) to be output at rclk, rpos/rneg (rdata). inputs to the transmitter are still transmitted on ttip and rclk latn 1 2 3 4 5 latn = 1 rclk, 9.5 db of attenuation latn = 2 rclk, 1 9.5 latn = 3 rclk, 28.5 db of attenuation latn = 4 rclk, 0 db of attenuation db of attenuation figure 7. latn pulse width encoding attenuation in db frequency in hz 10 20 30 40 50 60 1 10 100 1 k 10 k minimum attenuation limit measured performance 0 CS61318 figure 8. typical jitter transfer function
CS61318 ds441pp2 11 tring, unless taos has been selected, in which case ami-encoded continuous ones are transmitted at the tclk frequency. the receiver rtip and rring inputs are ignored when local loopback is in effect. 2.8 remote loopback remote loopback is selected by setting rloop, pin 26, high (cr1.5 = 1 in host mode). in remote loopback, the recovered clock and data input on rtip and rring are sent back out on the line via ttip and tring. selecting remote loopback over- rides a taos request. the recovered clock and data from the incoming signal are also sent to rclk, rpos and rneg (rdata). note: simultaneous se- lection of local and remote loopback modes will cause a device reset to occur (see reset). 2.9 network loopback network loopback (automatic remote loopback) can be commanded from the network when the network loopback detect function is enabled. in host mode, network loopback (nloop) detec- tion is enabled by writing ones to taos, lloop, and rloop, then clearing these three bits on a suc- cessive write cycle. in hardware mode, network loopback can be enabled by tying rloop to rclk or by setting taos, lloop, and rloop high for at least 200 ns, and then low. once enabled network loopback functionality will remain in ef- fect until rloop is activated or the device is reset. when nloop detection is enabled, the receiver monitors the input data stream for the nloop data patterns (00001 = enable, 001 = disable). when an nloop enable data pattern is repeated for a mini- mum of five seconds (with less than 10e-3 ber), the device initiates a remote loopback. once net- work loopback detection is enabled and activated by the nloop data pattern, the loopback is identi- cal to remote loopback initiated at the device. nloop is reset if the disable pattern (001) is re- ceived for 5 seconds, or by activation of rloop. nloop is temporarily suspended by lloop, but the nloop state is not reset. 2.10 alarm indication signal the receiver sets the register bit, ais, to 1 when less than 9 zeros are detected out of 8192 bit peri- ods. ais returns to 0 upon the first read after the ais condition is removed, determined by 9 or more zeros out of 8192 bit periods. 2.11 serial interface in the host mode, pins 24 through 28 serve as a mi- crocontroller interface. on-chip registers can be written to via the sdi pin or read from via the sdo pin at the clock rate determined by sclk. through these registers, a host controller can be used to con- trol operational characteristics and monitor device status. the serial port read/write timing is indepen- dent of the system transmit and receive timing. data transfers are initiated by taking the chip select input, cs , low (cs must initially be high). address and input data bits are clocked in on the rising edge of sclk. the clock edge on which output data is stable and valid is determined by clke as shown in table 1. data transfers are terminated by setting cs high. cs may go high no sooner than 50 ns after the rising edge of the sclk cycle corresponding to the last write bit. for a serial data read, cs may go high any time to terminate the output and set sdo to high impedance. figure 9 shows the timing relationships for data transfers when clke = 0. when clke = 1, data bit d7 is held until the falling edge of the 16th clock cycle. when clke = 0, data bit d7 is held valid until the rising edge of the 17th clock cycle. sdo goes high-impedance after cs goes high or at the end of the hold period of data bit d7. sdo goes to a high impedance state when not in use. sdo and sdi may be tied together in applica- tions where the host processor has a bi-directional i/o port.
CS61318 12 ds441pp2 an address/command byte, shown in figure 9, points to addresses 0x10 through 0x14 (address 0x10 shown), and precedes a data byte. the first bit of the address/command byte determines whether a read or a write is requested. the next six bits con- tain the address. the last bit is ignored. data to the internal registers is input on the eight clock cycles immediately following the address/command byte. cs sclk sdo clke = 0 sdi d6 d5 d4 d3 d2 d1 d0 d7 0 0 d7 d6 d5 d4 d3 d2 d1 d0 address/command byte data input/output 0 0 0 1 0 r/w figure 9. input/output timing (showing address 0x10) note: all control registers initialize to 0x00. 76543210addr control register 1 taos lloop rloop reserved set to 0 reserved set to 0 hdb3 nloop los 0x10 r/w control register 2 ais ramplse reserved set to 0 loopdn loopup rpwdn txhiz reserved set to 0 0x11 r/w equalizer gain (eqgain) x x x eq4 eq3 eq2 eq1 eq0 0x12 r arbitrary waveform ram address msb - - - - - - lsb 0x13 r/w reserved set to 0 0 0 0 0 0 0 0 0 0x14 table 2. register map
CS61318 ds441pp2 13 2.11.1 control register 1: address 0x10 taos transmit all ones select when taos = 1, all ones are transmitted at the tclk frequency lloop local loopback when lloop = 1, data input at tpos, tneg (tdata) is internally looped back and output on rpos, rneg (rdata). tclk is routed to rclk, through the jitter attenuator, if activated. rloop remote loopback when rloop = 1, clock and data recovered by the receiver are sent back through the transmit path and retransmitted. the clock and data are routed through the jitter attenuator, if activated. bits 4:3 reserved - set bits 3 & 4 to 0 for proper operation. hdb3 setting hdb3 to 1 enables hdb3 encoding and decoding. nloop network loopback nloop = 1 when a network loopback code has been detected on the received signal. an interrupt will occur when nloop changes state unless a 1 is written to nloop disabling the interrupt. los loss of signal los = 1 when the loss of signal criteria have been met (see receiver loss of signal). los = 0 when a valid signal is being received. writing a 1 to los disables interrupts due to los and the los change indication in bits 5 and 6. 7 (msb)6543210 (lsb) taos lloop rloop reserved set to 0 reserved set to 0 hdb3 nloop los
CS61318 14 ds441pp2 2.11.2 control register 2: address 0x11 ais alarm indication signal. ais = 1 when an all ones pattern is present at the receiver. this bit is reset to 0 by the first read occurring after the ais condition has cleared. an interrupt will occur when ais is present unless a 1 is written to ais disabling the interrupt. ramplse when ramplse = 1, output pulse shapes are determined by the codes in the internal, pro- grammable, transmit ram. rsvd reserved set to 0 for proper operation. loopdn loop down in long haul mode, setting loopdn to 1 causes the data pattern 001... to be repetitively transmitted. loopup loop up in long haul mode, setting loopup to 1 causes the data pattern 00001... to be repetitively transmitted. rpwdn receiver power down when rpwdn = 1, the receiver circuitry is powered down, but the transmitter is still active. txhiz transmitter high impedance when txhiz = 1 the transmitter goes to a low-power, high-impedance state 2.11.3 equalizer gain (eqgain): address 0x12 eq[4:0] the receive equalizer gain settings are broken down into 20 segments and provided at the five lsbs of this register, eq4 - eq0. 00001 corresponds to -2 db, 10100 corresponds to -40 db. the three msbs are dont cares. 2.11.4 arbitrary waveform ram address (ram): address 0x13 ram[7:0] arbitrary waveform ram; onboard ram is provided so that custom pulse shapes may be downloaded (see arbitrary waveform generation section). writing the waveform ram requires first writing the ad- dress/command byte with the write bit set (see figure 10) followed by a data byte which spec- ifies the ram address to be written. following these two bytes is a third byte that represents the waveform coefficient to be stored in the target address. there are 42 ram byte locations (numbered h00 to h29). 7 (msb) 6 5 4 3 2 1 0 (lsb) ais ramplse rsvd loopdn loopup rpwdn txhiz rsvd 7 (msb)6543210 (lsb) x x x eq4 eq3 eq2 eq1 eq0 7 (msb)6543210 (lsb) ram.7 ram.6 ram.5 ram.4 ram.3 ram.2 ram.1 ram.0
CS61318 ds441pp2 15 reading the control/status registers returns their current status or setting. control register 1 (0x10)) outputs the status of nloop and los. additional- ly, 5, 6, and 7 encoded as shown in tables 3. 2.12 interrupts an interrupt will occur (int pulls low) in response to a change in the los, ais or nloop bits. the interrupt is cleared when the host processor writes a 1 to the respective bit in the control register. writing a 1 to los or nloop over the serial in- terface has three effects: 1) the current interrupt on the serial interface will be cleared. (note that simply reading the register bits will not clear the interrupt). 2) output data bits 5, 6 and 7 will be reset as ap- propriate. 3) interrupts for the corresponding los and nloop will be prevented from occurring. writing a 0 to either los or nloop enables the corresponding interrupt for los and nloop. 2.13 power on reset / reset upon power-up, the ic is held in a static state until the supply crosses a threshold of approximately 3 volts. when this threshold is crossed, the device will delay for about 10 ms to allow the power sup- ply to reach operating voltage. after this delay, cal- ibration of the transmit and receive sections commences. because power up conditions can vary considerably, it is recommended that the device be reset after the power supply has stabilized to ensure a known initial operational condition. the internal frequency generators can be calibrated only if a reference clock is present. the reference clock for the transmitter is provided by tclk. the reference for the receiver is either the crystal oscil- lator or mclk. if both the oscillator and mclk are active, mclk will be used as the reference source. the initial calibration should take less than 20 ms after pulses are input to the receiver. in operation, the device is continuously calibrated, making the performance of the device independent of power supply or temperature variations. the continuous calibration function forgoes any re- quirement to reset the line interface when in opera- tion. however, a reset function is available which will reinitiate calibration and clear all registers and clear the network loopback function. in host mode, a reset is initiated by simultaneously writing rloop and lloop to the register. the re- set will set all registers to 0 and initiate a calibra- tion. a reset will also set los high in the short haul configuration. in hardware mode, the CS61318 is reset by simul- taneously setting rloop and lloop high for at least 200 ns. hardware reset will clear network loopback functionality 2.14 power supply the device operates from a single +5 volt supply. separate pins for transmit and receive supplies pro- vide internal isolation. these pins should be decou- table 3. control register 1 (0x10) decoding bits status mode 765 0 0 0 reset has occurred, or no program input 001rloop active 0 1 0 lloop active 0 1 1 los has changed state since last clear los occurred 100taos active 1 0 1 nloop has changed state since last clear nloop occurred 1 1 0 taos and lloop active 1 1 1 los and nloop have both changed state since last clear nloop and clear los
CS61318 16 ds441pp2 pled to their respective grounds. tv+ must not exceed rv+ by more than 0.3 v. decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. a 47 m f tantalum and 1.0 m f mylar or ceramic capacitor should be connected between tv+ and tgnd, and a 0.1 m f mylar or ceramic capacitor should be con- nected between rv+ and rgnd. place capacitors as closely as possible to their respective power sup- ply pins. wire-wrap breadboarding of the line in- terface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. 3 arbitrary waveform generation in addition to the predefined pulse shapes, the user can create custom pulse shapes under the host mode operation. this flexibility allows the board designer to accommodate non-standard cables, emi filters, protection circuitry, etc. the arbitrary pulse shape of mark (a transmitted 1) is specified by describing it's pulse shape across three unit intervals (uis). this allows, for example, the long-haul return-to-zero tail to extend into the next ui, or two uis, as is required for iso- lated pulses. each ui is divided into multiple phases, and the us- ers defines the amplitude of each phase. the wave- form of a space (a transmitted 0) is fixed at zero volts. examples of the phases are shown in figure 10. in all cases, to define an arbitrary wave- form, the user writes to the waveform register ei- ther 36, 39 or 42 times (12, 13 or 14 phases per ui for three uis). the phases are written in the order: ui1/phase1, ui1/phase2, ... , ui1/phase14, ui2/phase1, ... , ui2/phase14, ui3/phase1, ... , ui3/phase14. the CS61318 divides the 488 ns ui into 14 uni- form phases (34.9 ns each), and uses the phase in- formation written for all 14 phases of each ui. when transmitting pulses, the CS61318 will add the amplitude information from the prior two sym- bols with the amplitude of the first ui of the current symbol before outputting a signal on ttip/tring. therefore, a mark preceded by two spaces will be output exactly as the mark is programmed. howev- er, when one mark is preceded by marks, the first portion of the last mark may be modified. with ami data, where successive pulses have opposite polarity, the undershoot tail of one pulse will cause the rising edge of the next mark to rise more quick- ly, as shown in figure 11. e1 arbitrary waveform example figure 10. phase definition of arbitrary waveform figure 11. example of summing of waveforms
CS61318 ds441pp2 17 the amplitude of each phase is described by a 7-bit, 2's compliment number, where a positive value de- scribes pulse amplitude, and a negative value de- scribes pulse undershoot. the positive full value is hex 3f. the negative full value is hex 40. for e1 shielded twisted pair, the typical output voltage is 27 mv/lsb. all voltages are peak voltages across the ttip and tring outputs. using the circuits given in the applications section of the data sheet, the output impedance of the de- vice will be approximately equal to the impedance of the line. this means that the voltage on the trans- former secondary will be twice the values stated above. note that although the full scale digital in- put is 3f, it is recommended that full scale output voltage on the transformer primary be limited to 2.4 vpk. at higher output voltages, the driver may not drive the requested output voltage. the amplitude information for all phases is written via the serial-port to arbitrary waveform ram registers (see arbitrary waveform ram register for description). each phase amplitude is written as an eight-bit byte, where the first phase of the sym- bol is written first. the contents of the arbitrary waveform ram can be verified by performing a read operation. read- ing the waveform ram requires first writing the address/command byte with the r/w bit set to 1 (see figure 10) followed by a data byte which specifies the ram address to be read. on subse- quent sclks the contents of the specified ram location will be clocked out on sdo. notes: 1. in hardware mode the diagnostic modes are selected by directly setting the pins on the device; in host mode, the appropriate register bits are written for diagnostic modes. 2. in host mode the interrupts can be masked by writing a 1 to the los bit; there is no masking in the hardware mode. diagnostic mode availability (note 1) h/w host host mode (note 2) maskable loopback modes local loopback (lloop) yes yes no remote loopback (rloop) yes yes no in-band network loopback (nloop) yes yes yes internal data pattern generation and detection transmit all ones (taos) yes yes no in-band loop-up/down code generator no yes no error detection bipolar violation detection (bpv) yes yes no alarm condition monitoring receive loss of signal monitoring (los) yes yes yes receive alarm indication signal monitoring (ais) no yes yes other diagnostic reports receive line attenuation indicator (latn) yes yes no table 4. CS61318 diagnostic mode availability
CS61318 18 ds441pp2 turns ratio: 120 w twisted pair application 1:2 step-up transmit, 1:1 receive turns ratio: 75 w twisted pair application 1:1.58 step-up transmit, 1:1 receive table 5. transformer specification turns ratio(s) manufacturer part number package type 1:1ct pulse engineering pe-64936 1.5 kv, through-hole, single valor pt5008 schott 67130840 valor st5085 1.5 kv, surface mount, single schott 31187 1:2ct pulse engineering pe-65351 1.5 kv, through-hole, single valor pt5004 schott 617130850 valor st5086 1.5 kv, surface mount, single schott 31188 1:1ct 1:2ct pulse engineering pe-68678 1.5 kv, surface mount, dual valor st5162 pulse engineering pe-68877 1.5 kv, surface mount, dual extended temp. pulse engineering t-1068 1.5 kv, surface mount, quad port valor st5173 pulse engineering t-1031 3 kv, surface mount, dual 1:1.58 ct pulse engineering t-1229 1.5 kv, through hole, single table 6. recommended tranformers for the CS61318
CS61318 ds441pp2 19 4 pin description mclk taos/clke tclk lloop/sclk tpos/tdata rloop/cs tneg/ubs sdo mode sdi rneg/bpv nloop/int rpos/rdata rgnd rclk rv+ xtalin rring xtalout rtip jasel latn los nc ttip tring tgnd tv+ top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 mclk tclk taos/clke tpos/tdata lloop/sclk tneg/ubs rloop/cs mode sdo rneg/bpv sdi rpos/rdata nloop/int rclk rgnd xtalin rv+ xtalout rring jasel rtip los latn ttip nc tgnd tring tv+
CS61318 20 ds441pp2 4.1 power supplies tv+ - power supply, transmit driver, pin 15. power supply for the transmit driver; typically +5 volts. tgnd - ground transmit driver, pin 14. power supply ground for the transmit driver; typically 0 volts. rv+ - power supply, pin 21. power supply for all subcircuits except the transmit driver; typically +5 volts. rgnd - ground, pin 22. power supply ground for all subcircuits except the transmit driver; typically 0 volts. 4.2 oscillator xtalin, xtalout - crystal connections, pins 9 and 10. a 8.192 mhz crystal can be connected across these pins. this oscillator provides the reference frequency for the liu if mclk is not provided. the load capacitance presented to the crystal by these pins should be approximately 19pf (ic and package, when soldered into a circuit board). the jitter attenuator may be disabled by tying pin 9 to rv+ through a 1k w resistor, and floating xtalout. when pin 9 has no clock input, a clock must be supplied to the mclk pin. alternatively an external 8.192 mhz clock can be driven into pin 9, and the jitter attenuator circuit will operate. if mclk is provided, and xtalin is tied low or floated, the jitter attenuator will be enabled. 4.3 control mclk - master clock input, pin 1. either mclk or the crystal oscillator provide the master frequency reference for the CS61318. if both mclk and the crystal oscillator are present, the oscillator is ignored. mclk should be 2.048 mhz for e1 operation. in a loss of signal state, rclk will be derived from mclk, through the jitter attenuator, if active. if mclk is not provided, the jitter attenuator will hold the rclk frequency in a loss of signal state. mclk should be grounded if it is not used. mode - mode select input, pin 5. setting the mode pin high puts the CS61318 into host mode where the device is controlled by a microprocessor, via a serial port. setting the mode pin low, configures the part for hardware mode control where control and status are provided through dedicated pins. the mode pin is internally pulled down placing the part in hardware mode when this pin is left floating. tying the mode pin to rclk places the chip in hardware mode and enables the hdb3 encoder/decoder (provided that coder mode has been enabled; see the description for tneg/ubs pin). taos - transmit all ones select input, pin 28 (hardware mode). setting taos to logic 1 causes continuous ones to be transmitted at the tclk frequency. when taos is high, tpos and tneg (tdata) are not output at the ttip/tring pins. taos is overridden by remote loopback. setting taos, lloop, and rloop high simultaneously enables network loopback detection.
CS61318 ds441pp2 21 lloop - local loopback input, pin 27(hardware mode). setting lloop to a logic 1 internally routes the transmitter input to the receiver output. if taos is low, the signal being output from the transmitter will be internally routed to the receiver inputs allowing nearly the entire chip to be tested. if taos and lloop are set high at the same time, the local loopback will occur at the jitter attenuator (excluding the transmit and receive circuitry) and the transmitter will transmit all ones. simultaneously setting rloop and lloop high while taos is low resets the CS61318. simultaneously setting rloop, lloop and taos high enables network loopback detection. rloop - remote loopback input, pin 26 (hardware mode). setting rloop to a logic 1 causes the received signal to be passed through the jitter attenuator (if active) and retransmitted onto the line. the internal encoders/decoders will be bypassed in remote loopback. simultaneously setting rloop and lloop high while taos is low resets the CS61318. simultaneously setting rloop, lloop and taos high enables network loopback detection. jasel - jitter attenuator select, pin 11. if the jitter attenuator is enabled (crystal oscillator active, or xtalin tied low or floated with mclk provided), setting jasel high places the jitter attenuator in the receive path; setting jasel low places the jitter attenuator in the transmit path. nc - no connect, pin 17. the input voltage to this pin does not effect normal operation. 4.4 status los - loss of signal output, pin 12. los goes high when 175 consecutive zeros are received. los returns low when the ones density reaches 12.5% (based on 175 consecutive bit periods, starting with a one and containing less than 100 consecutive zeros, as prescribed in itu-t g.775). if los is true, and the jitter attenuator is in the receive path, rclk will smoothly transition to mclk if provided; rclk will retain the frequency prior to los if mclk is grounded. if the jitter attenuator is not in the receive path, rclk will become the reference clock frequency (mclk) if provided, or the crystal oscillator. nloop - network loopback output, pin 23 (hardware mode). nloop goes high when a 00001 pattern is received for five seconds putting the CS61318 into network (remote) loopback. nloop is deactivated upon receipt of a 001 pattern for five seconds, or by selection of lloop or rloop. latn - line attenuation indication output, pin 18. latn is an encoded output that indicates the receive equalizer gain setting in relation to a five rclk cycle period. if latn is high for one rclk cycle, the equalizer is set for 9.5 db gain, two cycles = 19.5 db gain, three cycles = 28.5 db gain, four cycles = 0 db. latn may be sampled on the rising edge of rclk. 4.5 serial control interface int - interrupt output, pin 23 (host mode). int pulls low to flag the host processor when nloop, ais or los changes state. int is an open drain output and should be tied to the supply through a resistor.
CS61318 22 ds441pp2 sdi - serial data input, pin 24 (host mode). data input to the on-chip register is sampled on the rising edge of sclk. note: this pin should be tied to gnd during hardware mode. sdo - serial data output, pin 25 (host mode). status and control information are output from the on-chip register on sdo. if clke is high, sdo is valid on the rising edge of sclk. if clke is low, sdo is valid on the falling edge of sclk. sdo goes to a high-impedance state when the serial port is being written to, or after bit d7 is output or cs goes high (whichever occurs first). note: this pin should be tied to gnd during hardware mode. cs - chip select, pin 26 (host mode). the serial interface is accessible when cs transitions from high to low. sclk - serial clock input, pin 27 (host mode). sclk is used to write or read data bits to or from the serial port registers. clke - clock edge, pin 28 (host mode). setting clke to logic 1 causes rpos and rneg (rdata) to be valid on the falling edge of rclk, and sdo to be valid on the rising edge of sclk. conversely, setting clke to logic 0 causes rpos and rneg (rdata) to be valid on the rising edge of rclk and sdo to be valid on the falling edge of sclk. 4.6 data input/output tclk - transmit clock input, pin 2. the 2.048 mhz transmit clock is input on this pin. tpos and tneg or tdata are sampled on the falling edge of tclk. tpos/tneg - transmit positive pulse, transmit negative pulse, pins 3 and 4. data input to tpos and tneg is sampled on the falling edge of tclk and transmitted onto the line at ttip and tring. an input on tpos results in transmission of a positive pulse; an input on tneg results in transmission of a negative pulse. if tneg, pin 4, is held high for 16 tclk cycles, the CS61318 reconfigures for unipolar (single pin nrz) data input at pin 3, tdata. if pin 4 goes low the CS61318 switches back to two-pin bipolar data input format. tdata - transmit data, pin 3. when pin 4, tneg/ubs, is held high, pin 3 becomes tdata, a single-line nrz (unipolar) data input sampled on the falling edge of tclk. ubs - unipolar / bipolar select, pin 4. when ubs is held high for 16 consecutive tclk cycles (15 consecutive bipolar violations) the CS61318 reconfigures for unipolar (single-line nrz) data input / output format. pin 3 becomes tdata, pin 7 becomes rdata, and pin 6 becomes bpv. rclk - recovered clock output, pin 8. rclk outputs the clock recovered from the input signal at rtip and rring. in a loss of signal state rclk reverts to the mclk frequency, or retains the frequency prior to the los state, depending on the clocks provided. see the los pin description.
CS61318 ds441pp2 23 rneg/rpos - receive negative pulse, receive positive pulse, pins 6 and 7. recovered data output on rpos and rneg is stable and valid on the rising edge of rclk in hardware mode. in host mode, clke determines the edge of rclk on which rpos and rneg are valid. a positive pulse on rtip with respect to rring generates a logic 1 on rpos; a positive pulse on rring with respect to rtip generates a logic 1 on rneg. rdata - received data, pin 7. unipolar data (single-line nrz) data is output on rdata when pin 4, tneg/ubs, is held high. bpv - bipolar violation, pin 6. when pin 4 is held high, received bipolar violations are flagged by bpv (rneg) going high along with the offending bit output from rdata. if the hdb3 encoder/decoder is activated, bpv will not flag bipolar violations resulting from valid zero substitutions. rtip,rring - receive tip; receive ring, pins 19,20. the hdb3 signal received from the line is input via these pins. a 1:1 transformer and appropriate matching resistors are required as shown in the applications section. data and clock recovered from the signal input on these pins is output via rpos, rneg, and rclk. ttip, tring - transmit tip; transmit ring, pins 13,16 these pins are the output of the differential transmit driver. the transformer and matching resistors can be chosen to give the desired pulse height (see application schematics).
CS61318 24 ds441pp2 5 package dimensions 1. positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e does not include mold flash. inches millimeters dim min max min max a 0.155 0.200 3.94 5.08 a1 0.020 0.040 0.51 1.02 b 0.014 0.022 0.36 0.56 b1 0.040 0.065 1.02 1.65 c 0.008 0.015 0.20 0.38 d 1.435 1.465 36.45 36.83 e 0.540 0.560 13.72 14.22 e 0.095 0.105 2.41 2.67 ea 0.600 0.625 15.24 15.87 l 0.125 0.150 3.18 3.81 0 15 0 15 28 pin plastic (pdip) package drawing e d seating plane b1 e b a l a1 top view bottom view side view 1 ea c
CS61318 ds441pp2 25 inches millimeters dim min max min max a 0.165 0.180 4.043 4.572 a1 0.090 0.120 2.205 3.048 b 0.013 0.021 0.319 0.533 d 0.485 0.495 11.883 12.573 d1 0.450 0.456 11.025 11.582 d2 0.390 0.430 9.555 10.922 e 0.485 0.495 11.883 12.573 e1 0.450 0.456 11.025 11.582 e2 0.390 0.430 9.555 10.922 e 0.040 0.060 0.980 1.524 jedec #: ms-018 28l plcc package drawing d1 d e1 e d2/e2 b e a1 a
CS61318 26 ds441pp2 6 applications control & monitor frame format encoder/ decoder CS61318 in host mode receive line 28 1 12 6 5 7 6 8 3 4 2 9 10 rv+ + 33 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ clke mclk los bpv mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 sclk cs int sdi sdo rtip rring tring ttip 19 20 r1 r2 1 5 2 6 t1 1:1 m p serial port 27 26 23 24 25 18 latn 1k w 11 jasel 0.47 m f t2 1:n transmit line 16 13 0.47 m f 2 6 1 5 r3 r4 figure 12. CS61318 host mode operation note: the 0.47 m f capacitor between r1 & r2 may be omitted if common mode noise is not an issue. note: the optional 0.47 m f dc blocking cap eliminates dc saturation current through t2 e1 75 w coaxial cable e1 120 w twisted pair r1 ( w ) 37.5 60 r2 ( w ) 37.5 60 r3 ( w ) 15 15 r4 ( w ) 15 15 t2 1:1.58 1:2
CS61318 ds441pp2 27 control & monitor frame format encoder/ decoder CS61318 in hardware mode 28 1 26 27 5 7 6 8 3 4 2 9 10 + 33 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ taos mclk rloop lloop mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 rtip rring tring ttip 24 25 12 23 los nloop 11 jasel receive line 19 20 r1 r2 1 5 2 6 t1 1:1 0.47 m f transmit line 16 13 0.47 m f 2 6 1 5 r3 r4 sd i sdo t2 1:n figure 13. hardware mode configuration note: the 0.47 m f capacitor between r1 & r2 may be omitted if common mode noise is not an issue. note: the optional 0.47 m f dc blocking cap eliminates dc saturation current through t2 e1 75 w coaxial cable e1 120 w twisted pair r1 ( w ) 37.5 60 r2 ( w ) 37.5 60 r3 ( w ) 15 15 r4 ( w ) 15 15 t2 1:1.58 1:2

▲Up To Search▲

Price & Availability of CS61318

	To Download CS61318 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .